Vyatta documentation

Learn how to install, configure, and operate the Vyatta Network Operating System (Vyatta NOS) and Orchestrator, which help drive our virtual networking and physical platforms portfolio.

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The dataplane is a combination of the DPDK based software forwarding pipeline and the FAL interface to hardware forwarding pipelines.

It provides the necessary mechanisms for bridging the DPDK pipeline with switching silicon based on user configuration.


The processing pipeline is a design used to encapsulate processing stages into discrete processing blocks, with standard defined input/outputs.

The reason for this processing is to allow both runtime and compile time shaping of the processing path for packet flow. Currently, behavior exists as a run to completion model, for performance, but with re-configurable stages. 

Additional benefits provide for improved packet performance analysis and debugging as well as promoting software reuse.


The FAL is the integration point for hardware switch devices.

This provides a generic set of APIs for the dataplane to program the hardware switch. Vendor specific code is written into FAL plugins which are loaded dynamically at runtime. 

The two key design principles of the FAL are:

  • Keep the platform dependencies in the FAL plugin as much as possible

  • Keep state out of the FAL plugin as much as possible, to keep the FAL plugin as simple as possible

The FAL abstracts the platform as much as possible to allow the application to be independent of platform specifics.

The implementation of the FAL plugin would ideally place as much of the platform specifics into data files, rather than in the code, in order to allow new platforms to be integrated quickly. A new piece of platform functionality that interacts with the switch chip may require new code and platform data parsing to use it.